Multi-function semiconductor devices can be fabricated by mounting a semiconductor nonvolatile memory cell on the same substrate with a logic semiconductor device. These multifunction semiconductor devices are widely utilized as built-in type microcomputers in industrial machinery, home appliances, and automobiles, etc.
These types of nonvolatile memories generally store a program required by that microcomputer are used to read out that program whenever needed. The cell structure of the nonvolatile memory for mounting along with these types of logic semiconductor devices are described as split-gate memory cells made up of selection MOS transistors and memory MOS transistors.
In order to employ source-side-injection (SSI) possessing good charge injection efficiency, this structure is designed for joint applications including high-speed writing, and providing a reduction in peripheral circuit area comprised of low-voltage transistors with a small device area as the memory cell selection transistors and transistors connecting to those memory cell transistors. Technical documents of the known art relating to this technology include for example, patent document 1, patent document 2, non-patent document 1, non-patent document 2, and non-patent document 3.
Method for retaining the electrical charge within the memory MOS transistor are: the floating gate type method (patent document 2, non-patent document 1) where the electrical charge is stored in electrically isolated conductive polysilicon, and the MONOS method (patent document 1, noon-patent document 2) for storing the electrical charge in an insulator film possessing properties similar to charge trapping properties of silicon nitride film.
The floating gate method possesses good charge retention characteristics and is widely utilized in large-capacity data storage flash memories and program storage flash memories for cellular telephones, etc. However, maintaining the charge coupling rate needed for controlling the voltage potential became more difficult in the floating gate as device integration became advanced, and the structure became more complicated. The oxide film enclosing the floating gate must be at least 8 nanometers thick in order to suppress leakage of the stored electrical charge, and the floating gate is approaching its miniaturization limits in term of high-speed and high-integration. If there is a flaw causing a leak path in even one position on the oxidized film around the floating gate, then the electrical charge retention of the floating gate drastically decreases.
In the MONOS system on the other hand, the electrical charge retention is generally poor compared to the floating gate, and the threshold voltage tends to drop with the logarithm of the time. Therefore, while this method has been known from a long time past its use is limited to only certain products.
However, a localized charge trapping method is utilized to hold the electrical charge in an insulating element so that even if there are several leak paths, there is few loss of the overall charge being held so the MONOS method is strongly resistant to defects in the oxidized film. Oxidized film thinner than 8 nanometers can therefore be used so this (MONOS) method is more suited to miniaturization and the probability of a drastic drop in the charge retention due to a defect is low so reliability can be easily predicted. Moreover, the memory cell structure is simple and can be easily mounted with logic circuits so that this method is again the focus of attention in recent years as device scaling is advanced.
The split-gate structure which is particularly well suited for scaling, is a side wall structure (patent document 1, non-patent document 2) in which a side wall is utilized to form a MOS transistor gate electrode from one of the MOS transistors utilized for self-alignment. In this case, the gate length of the transistor formed by self-alignment can be formed less than minimum lithographic resolution dimensions so that a tiny memory cell can be formed compared to the method of the conventional art which forms two transistors with photomask.
Even among split-gate memory cells using self-alignment, those cells formed with a MONOS structure on the self-aligning gate as disclosed for example in patent document 3, non-patent document 2, are ideal to be embedded with high speed logic circuits.
A cross sectional view of this memory cell is shown in FIG. 1. The memory gate electrode 11 is formed from an ONO film (oxide film/nitride film/oxide film) of SiO2 film 13, SiN film 14, SiO2 film 15 on the side wall of the selection gate electrode 12 and a polysilicon electrode with a side wall structure. A silicide layer 16 is formed on the upper section of the diffusion area 1 and 5, and selection gate electrode 12, and memory gate electrode 11.
In order to first form the selection gate electrode of this memory cell structure, the gate oxide film of the logic circuit section transistor can be formed simultaneously, with the selection gate electrode in a state where the silicon substrate surface (interface) is of good quality. A sensitive high-speed operation thin-film gate transistor with good interface quality can be formed first so the selection transistor and the transistors of the logic circuits possess better performance. The loading (reading) of the stored information can be performed just by high-performance selection transistor operation and their connecting transistors can all be thin-film low-voltage types so fast loading (read-out) can be achieved and the circuit area is reduced.
The memory cell array structure possessing these split-gate type MONOS memory transistors is shown in FIG. 2. Each cell and the opposing memory cell jointly possess a semiconductor region (highly doped region, hereafter called the source) adjoining the memory gate electrode 11; and the source line 1 is in parallel with the word line. Two types of word lines for the selection gate 3 and for the memory gate 2 extend in parallel toward the word lines. The bit lines 4 perpendicular to these word lines, connect to the semiconductor region (highly doped region, hereafter called the drain) adjoining the selection gates 12 of each cell.
Voltage conditions during typical operation are shown in FIG. 3. In the write operation, the semiconductor surface directly below the selection gate 3 is set to weak inversion state with approximately 12 volts and 5 volts applied to memory gate 2 and the source 1 by the source side injection method (SSI method), and hot electrons are injected into the silicon nitride film serving as the charge trapping film of the ONO film, by the strong electrical field occurring between the semiconductor substrate surface and the memory gate 2.
In the erase operation, the hot hole injection method (BTBT method) via a tunnel between bands is utilized. A voltage of approximately −5 volts is applied to the memory gate 2 and 7 volts is applied to the source 1 as a reverse bias, and the strong electric field on the edge of the diffusion area generates hot holes via the tunneling between bands, and these hot holes are injected into the memory gate 2. To read information, 1.5 volts is applied to both the memory gate 2 and selection gate 3, and 1 volt is applied to the drain (bit line 4), and the read information determined by amplitude of the current flowing in the drain (bit line 4).
The process for manufacturing the memory cell containing split-gate type MONOS memory transistors is characterized by good compatibility with the standard CMOS process, and can be used to mount components such as microcomputers on the semiconductor memory. The process flow compatible with when mounting via the standard CMOS process is shown utilizing FIG. 4 through FIG. 10.
FIG. 4 is a cross-section view of the stage for forming the gate electrode structure of polysilicon on the silicon substrate. Though not shown in the figure, in the previous stage, the structure of the field isolating insulator is formed utilizing the conventional method, and the gate insulator film and polysilicon gate electrode material films are formed. The memory area selection transistor and the logic area transistors have the gate insulator in common. The reference numeral 12 denotes the selection gate electrode, and the reference numeral 17 denotes the gate electrode for the logic area transistor.
The stage for forming the three-layer ONO film 18 structure of SiO2 film, SiN film, SiO2 film is next shown in FIG. 5.
The second polysilicon is deposited as the memory gate electrode material and, etchback performed by dry etching to leave polysilicon film as the side wall electrode only on the side of the gate electrode as shown in the state in FIG. 6. The reference numeral 20 denotes the contact extension, reference numeral 40 is the memory gate side wall electrode removed later, and reference numeral 41 is the logic area side wall electrode removed later. Among the side wall electrodes that were formed, the unnecessary side wall electrode 40 on one side, and the side wall electrode 41 on both sides of the logic area are removed by etching, and when the ONO film whose lower layer of polysilicon was removed, and the ONO film formed on the upper surface of the select electrode 12 are removed the state shown in FIG. 7 is attained. The ONO film formed on the upper surface of the select gate electrode 12 is removed in order to simultaneously silicide the upper surface of the select gate electrode 12 and lower the resistance of the select gate electrode 12, so that the resistance of the memory gate to be formed is lowered during siliciding.
At this point, the SiO2 film forming the side wall of the logic area transistor and the MONOS memory cell is deposited and etched back to form the state in FIG. 8. Reference numeral 19 is the oxide film side wall. The state where siliciding was performed to lower the resistance of the gate electrode and diffusion area is shown in FIG. 9. Reference numeral 27 is the silicided section. The first layer of a resistive film 42 is then deposited, and the stage after planarizing and forming of the contact areas is shown in FIG. 10. The description of the standard process for forming the metal wiring layers of approximately three to six layers is omitted.
The masks required for embedding nonvolatile memories in the related art can be broadly grouped into masks for ion injection, and structural forming masks. Of these mask types, one structural forming mask is utilized for removing the polysilicon side wall electrode on one side of the selection gate; and another structural forming mask is utilized for forming the wiring contact areas to the memory gate electrode. Of these structural forming masks, the latter mask is intended only for forming the contact area with the wiring, regardless of the fact that the memory gate electrode is formed by self-alignment and essentially does not require a mask.
The contact forming section is next described in further detail. The layout of the contact forming region (connecting) to the memory gate electrode in the technology of the related art is shown in FIG. 11. One word line formed from the memory gate and the select gate extends to the device isolation region and forms the contact area.
In the technology of the related art as shown in FIG. 7, the ONO film on the upper surface of the select gate 12 must be removed in order to silicide the selection gate electrode 12 and memory gate electrode 11 in the same process. However as shown in FIG. 10, the first layer of the insulator film 42 is common with on the selection gate electrode 12 and on the memory gate electrode 11 after the siliciding, so that when forming the contact hole on the insulator film 42 for receiving the contact on the memory gate electrode 11, the surface of the selection gate electrode 12 might become exposed rather than just the surface of the memory gate electrode 11.
This unwanted exposure is caused by the fact that the width of the memory gate electrode is approximately 60 nanometers and the memory gate electrode is a side wall electrode that is small compared to the width of the contact hole; and the fact that the selection gate electrode 12 and the memory gate electrode 12 are only separated by a distance 20 nanometers as the thickness of the ONO film 18; and the fact that the photolithography alignment error in the process for forming the contact hole is approximately 60 nanometers which is the same as the width of the memory gate electrode 11.
When forming the contact hole in this way, and the surface of the memory gate electrode 11 and the surface of the selection gate electrode 12 are exposed within one contact hole, the forming of the contact might cause the memory gate electrode 11 and selection gate electrode 12 to short and disable the nonvolatile memory.
To eliminate this possibility, a dedicated contact region 20 is formed by photolithography as shown in FIG. 11. This contact region 20 is formed by utilizing a dedicated mask, and covering just the contact region 20 with photoresist during etchback of the memory gate electrode so that a section with no etchback is formed. The reference numeral 21 is the contact. The line taken along A-A′ in the cross sectional view in FIG. 11 is jointly recorded in FIG. 12, and the manufacturing process flow for the memory area and the logic area are jointly described in FIG. 4 through FIG. 10. The contact region 20 can in this way be formed at a position isolated from the selection gate electrode 12 so that the contact 21 for the memory gate electrode 11 as described above, does not connect to the selection gate electrode 12, and the memory gate electrode 11 is prevented from shorting to the selection gate electrode 12. In FIG. 11, the contact region 20 overlaps onto the selection gate electrode 12 however as clearly shown in the cross sectional view in FIG. 12, an ONO film is formed between the contact region 20 and the selection gate electrode 12 so that because of the electrical insulation, there will be no shorts. A technology for forming a contact auxiliary pattern as a technique for reducing the masks for the split-gate type nonvolatile memory is disclosed in FIG. 1 and FIG. 2 of the patent document 4.    [Patent document 1] JP-A No. 48113/1993    [Patent document 2] JP-A No. 121700/1993    [Patent document 3] JP-A No. 186452/2004    [Patent document 4] JP-A No. 326286/2001    [Non-patent document 1] IEEE, 1994 Symposium on VLSI Technology, Review pp. 71-72    [Non-patent document 2] IEEE, 1997 Symposium on VLSI Technology, Review pp. 63-64    [Non-patent document 3] IEEE, 2003 Symposium on VLSI Circuits Digest of Technical Papers, Session No. 16, Academic paper No. 2.